Recently, research teams from the Massachusetts Institute of Technology, the University of Houston, and other institutions in the United States have discovered the best semiconductor materials to date. This material is called cubic boron arsenide, which provides high mobility for electrons and holes, excellent conductivity, and extremely high thermal conductivity. The relevant achievements have been published in the recent journal Science, and the author column includes multiple Chinese individuals, including Chen Gang, a professor of mechanical engineering at the Massachusetts Institute of Technology, and Ren Zhifeng, a professor at the Chinese Academy of Sciences (University of Houston).   It is worth noting that cubic boron arsenide can only be produced and tested on a small-scale scale in the laboratory, and is uneven. Scientists still need to do more w...

Recently, according to news on the official website of Fudan University, the Fudan team has invented a wafer level silicon based two-dimensional complementary stacked transistor   Traditional integrated circuit technology uses planar unfolded electronic and hole transistors to form complementary structures, thereby achieving high-performance computing power. The increase in density is mainly achieved by reducing the size of the unit transistor.   For example, industries below 7nm nodes use extreme ultraviolet lithography technology to achieve high-precision size reduction. The complexity of extreme ultraviolet lithography equipment highlights the value of three-dimensional stacked complementary transistor (CFET) technology, which can significantly improve the integration density under existing technological nodes. However, the process complexity of all silicon base...

On March 1st, global semiconductor solution provider Reza Electronics announced the launch of a new breakthrough cloud based online IoT system design platform, Quick Connect Studio, to help users build hardware and software in a graphical manner, quickly validate prototypes and accelerate product development.   The current software development process is very cumbersome - engineers need to study and define projects, collect equipment information and requirements, lay out hardware, develop software, and test and iterate until the product is ready for release to the market. This process is usually carried out in sequence, and each step requires a significant amount of time. For the development of new products, the development of the software part is the most consumed stage, and whether the development process is smooth becomes a key factor determining the success or failur...

Currently, major semiconductor research and development institutions and enterprises around the world have carried out a lot of work on the SOT-MRAM etching process. However, the etching process of SOT-MRAM remains an important technical challenge faced by the industry.   Recently, the Institute of Microelectronics of the Chinese Academy of Sciences has made new progress in the key integration technology field of SOT-MRAM.   According to the "Institute of Microelectronics, Chinese Academy of Sciences", in order to better solve the problem of SOT-MRAM etching technology to achieve high density integration on the chip of SOT-MTJ, and at the same time to study the impact of different etching processes on the magnetoelectric characteristics of devices, Luo Jun, a research team of the Research Center of Integrated Circuit Pilot ...

According to foreign media reports, Armor and Western Data plan to showcase 3D NAND technology innovation at the 2023 VLSI Technology and Circuit Seminar.     Engineers from both companies are seeking to implement 8-Plane 3D NAND and over 300 layers of 3D NAND. The paper (C2-1) from Armor introduces an 8-Plane 1Tb 3D TLC NAND with a stack count of 210 layers and an I/O speed of 3.2GT/s, which is very similar to the 218 layer 1Tb 3D TLC NAND launched by Armor/Western Data and has a 17Gb/mm performance ² Density and 3.2GT/s I/O bus, but it is 8-Plane instead of 4-Plane, and it is said to provide a Program Throughput of 205MB/s and 40 μ The read latency of s is significantly better than that of Armor 128 layer 3D NAND, which is 56 μ S delay.。   In addition to studying the 3DNAND str...